An embedded system is generally a specialized computer system that performs a special purpose and that may be a subsystem in a larger system. Often, an embedded system is provided on a single, inexpensive integrated circuit chip that includes a microcontroller or microprocessor and associated memory. The associated memory includes an EEPROM and other types of memories. A write operation for an EEPROM takes much greater time than a read operation for an EEPROM. A typical write time for an embedded EEPROM is several milliseconds, while a typical read time is 10 to 100 nanoseconds. As a consequence of the greater write time for an EEPROM, a typical processor that is associated with an EEPROM in an embedded system is required to stop and then wait a considerable amount of downtime for each write operation to the EEPROM.
A typical EEPROM write operation includes the following steps: a page buffer for the EEPROM is loaded with one or more bytes of data. A voltage on a control pin is changed to start the write operation by writing from the page buffer to the memory cells. Upon completion of the write operation, an EPROM BUSY bit is reset to indicate completion of the EEPROM write operation.
In a typical embedded EEPROM, the EEPROM is not available for read/write operations until the EEPROM BUSY bit is reset, or goes away. This results in the processor waiting (either by polling the EEPROM BUSY bit, or by an interrupt) until EEPROM BUSY bit is reset before continuing code execution. This is especially true in systems where code and data are stored in a single EEPROM. Requiring the processor to wait is very common in embedded systems where both program code and data are stored in a single EEPROM.
In an embedded system that has more than one type of memory, read/write operation can be optimized in such a way that the processor can continue to do useful work during the time that the EEPROM is in a write cycle. Such optimizations should make sure that, during the write operation, no EEPROM accesses will be needed by the computer. This requires that the computer does not fetch data from the EEPROM while EEPROM BUSY bit is asserted. In an embedded system, it can become complicated trying to make such an optimization.
Alternatively, a simpler block-after-write approach is often used to write data into an EEPROM and then to block operation of the microprocessor while the write operation to the EEPROM is being completed. An example of code for a block-after-write subroutine is shown below:
// example of block-after-write codevoid eeWriteByte( uint16_t address, uint8_t data) {outb(IO_EECR, EEWRITE_FLAG;// set the EEPROM write bitin the control registeroutw (IO_EEAR, address);// write the address to the EEaddress registeroutb(IO_EEDR, data);// write the data to the EEdata registeroutb(IO_EECR, 0);// drop the write control linestarting the writewhile(inb(IO_EESTATUS) & EEBUSY_FLAG) {nop( ); // wait until busy goes away}}
FIG. 1 is a flowchart 100 for a block-after-write subroutine that blocks, or interrupts, operation of a computer after writing to an EEPROM. Block 102 shows that the block-after-write subroutine first sets the EEPROM WRITE bit in the control register. Block 104 shows that the subroutine then writes the designated EEPROM address to the EEPROM address register. Block 106 shows the subroutine then writes the data to the EEPROM data register. Block 106 shows that a WRITE CONTROL line is dropped to start writing the data from the EEPROM data register into the addressed EEPROM memory location. Block 110 indicates that the processor is blocked from operation by being in a wait state until the EEPROM write operation is complete and the EEPROM BUSY bit is deasserted.
At first thought you could move the blocking code to the beginning of the subroutine, but it has the result that any subsequent EEPROM reads would fail. Incorrect data would be read without any indication an error had occurred.
U.S. Patent Publication 2004/0208064 to Sohn et al. describes a method of controlling an IC memory that is capable of simultaneously performing a data read operation and a data write operation. However, this approach requires a memory with separate input and output pins and also uses a tag memory. Using additional hardware would not be cost effective in a embedded microcontroller system.
U.S. Pat. No. 5,657,467 to Hasegawa describes a non-volatile semiconductor memory device that includes a separate register for storing data. A selection circuit is supplied with a busy signal from a write control circuit, which indicates that the memory device is operating in a write mode and that an output signal from the separate register should be used. Having a separate register for storing data would not be cost effective in a embedded microcontroller system.
U.S. Pat. No. 6,512,693 to Honda et al. describes a memory cell array that is arranged into a number of cores, each of which includes a block of memory cells. A number of cores are selected as a first bank, while the remaining cores are selected as a second bank. This allows a data read operation to be carried on in one bank while a data write/erase operation is carried out in the second bank. Having a number of cores and block of memory would not be cost effective in an embedded microcontroller system
What is needed is an efficient technique for effectively reducing downtime for a processor associated with an EEPROM in an inexpensive embedded system.